Texas Instruments SimpleLink CC2620 Technical Reference Manual page 113

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2.7.3.25 STIM24 Register (Offset = 60h) [reset = X]
STIM24 is shown in
Stimulus Port 24
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 STIM24
SWCU117C – February 2015 – Revised September 2015
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Figure 2-58 and described in
Figure 2-58. STIM24 Register
Table 2-83. STIM24 Register Field Descriptions
Type Reset
R/W X
Copyright © 2015, Texas Instruments Incorporated
Table 2-83.
STIM24
R/W-X
Description
A write to this location causes data to be written into the FIFO if
TER.STIMENA24 is set. Reading from the stimulus port returns the
FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface
does not provide an atomic read-modify-write, so it's users
responsibility to ensure exclusive read-modify-write if this ITM port is
used concurrently by interrupts or other threads.
Cortex-M3 Processor Registers
9 8 7 6 5 4 3 2 1 0
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