Texas Instruments SimpleLink CC2620 Technical Reference Manual page 164

Cortex-M3 Processor Registers
2.7.4.25 NVIC_IPR8 Register (Offset = 420h) [reset = 0h]
NVIC_IPR8 is shown in
Irq 32 to 35 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bit Field
31-16 RESERVED
15-8 PRI_33
7-0 PRI_32
164
Figure 2-95 and described in
Figure 2-95. NVIC_IPR8 Register
R/W-0h
Table 2-121. NVIC_IPR8 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-121.
9
PRI_33
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details).
Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details).
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
PRI_32
R/W-0h
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