Prcm Registers - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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6.2.4 PRCM Registers

Table 6-44 lists the memory-mapped registers for the PRCM. All register offset addresses not listed in
Table 6-44 must be considered as reserved locations and the register contents must not be modified.
Offset Acronym
0h INFRCLKDIVR
4h INFRCLKDIVS
8h INFRCLKDIVDS
Ch VDCTL
28h CLKLOADCTL
2Ch RFCCLKG
30h VIMSCLKG
3Ch SECDMACLKGR
40h SECDMACLKGS
44h SECDMACLKGDS
48h GPIOCLKGR
4Ch GPIOCLKGS
50h GPIOCLKGDS
54h GPTCLKGR
58h GPTCLKGS
5Ch GPTCLKGDS
60h I2CCLKGR
64h I2CCLKGS
68h I2CCLKGDS
6Ch UARTCLKGR
70h UARTCLKGS
74h UARTCLKGDS
78h SSICLKGR
7Ch SSICLKGS
80h SSICLKGDS
84h I2SCLKGR
88h I2SCLKGS
8Ch I2SCLKGDS
B8h CPUCLKDIV
C8h I2SBCLKSEL
CCh GPTCLKDIV
D0h I2SCLKCTL
D4h I2SMCLKDIV
D8h I2SBCLKDIV
DCh I2SWCLKDIV
10Ch SWRESET
110h WARMRESET
12Ch PDCTL0
130h PDCTL0RFC
134h PDCTL0SERIAL
138h PDCTL0PERIPH
140h PDSTAT0
SWCU117C – February 2015 – Revised September 2015
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Table 6-44. PRCM Registers
Register Name
Infrastructure Clock Division Factor For Run Mode
Infrastructure Clock Division Factor For Sleep Mode
Infrastructure Clock Division Factor For DeepSleep
Mode
MCU Voltage Domain Control
Clock Load Control
RFC Clock Gate
VIMS Clock Gate
TRNG, CRYPTO And UDMA Clock Gate For Run Mode
TRNG, CRYPTO And UDMA Clock Gate For Sleep
Mode
TRNG, CRYPTO And UDMA Clock Gate For Deep
Sleep Mode
GPIO Clock Gate For Run Mode
GPIO Clock Gate For Sleep Mode
GPIO Clock Gate For Deep Sleep Mode
GPT Clock Gate For Run Mode
GPT Clock Gate For Sleep Mode
GPT Clock Gate For Deep Sleep Mode
I2C Clock Gate For Run Mode
I2C Clock Gate For Sleep Mode
I2C Clock Gate For Deep Sleep Mode
UART Clock Gate For Run Mode
UART Clock Gate For Sleep Mode
UART Clock Gate For Deep Sleep Mode
SSI Clock Gate For Run Mode
SSI Clock Gate For Sleep Mode
SSI Clock Gate For Deep Sleep Mode
I2S Clock Gate For Run Mode
I2S Clock Gate For Sleep Mode
I2S Clock Gate For Deep Sleep Mode
CPU Clock Division Factor
I2S Clock Control
GPT Scalar
I2S Clock Control
MCLK Division Ratio
BCLK Division Ratio
WCLK Division Ratio
SW Initiated Resets
WARM Reset Control And Status
Power Domain Control
RFC Power Domain Control
SERIAL Power Domain Control
PERIPH Power Domain Control
Power Domain Status
Copyright © 2015, Texas Instruments Incorporated
PRCM Registers
Section 6.2.4.1
Section 6.2.4.2
Section 6.2.4.3
Section 6.2.4.4
Section 6.2.4.5
Section 6.2.4.6
Section 6.2.4.7
Section 6.2.4.8
Section 6.2.4.9
Section 6.2.4.10
Section 6.2.4.11
Section 6.2.4.12
Section 6.2.4.13
Section 6.2.4.14
Section 6.2.4.15
Section 6.2.4.16
Section 6.2.4.17
Section 6.2.4.18
Section 6.2.4.19
Section 6.2.4.20
Section 6.2.4.21
Section 6.2.4.22
Section 6.2.4.23
Section 6.2.4.24
Section 6.2.4.25
Section 6.2.4.26
Section 6.2.4.27
Section 6.2.4.28
Section 6.2.4.29
Section 6.2.4.30
Section 6.2.4.31
Section 6.2.4.32
Section 6.2.4.33
Section 6.2.4.34
Section 6.2.4.35
Section 6.2.4.36
Section 6.2.4.37
Section 6.2.4.38
Section 6.2.4.39
Section 6.2.4.40
Section 6.2.4.41
Section 6.2.4.42
Power, Reset, and Clock Management
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