Texas Instruments SimpleLink CC2620 Technical Reference Manual page 153

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Table 2-111. NVIC_IABR0 Register Field Descriptions (continued)
Bit Field
20 ACTIVE20
19 ACTIVE19
18 ACTIVE18
17 ACTIVE17
16 ACTIVE16
15 ACTIVE15
14 ACTIVE14
13 ACTIVE13
12 ACTIVE12
11 ACTIVE11
10 ACTIVE10
9 ACTIVE9
8 ACTIVE8
7 ACTIVE7
6 ACTIVE6
5 ACTIVE5
4 ACTIVE4
3 ACTIVE3
SWCU117C – February 2015 – Revised September 2015
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Type Reset Description
R 0h
Reading 0 from this bit implies that interrupt line 20 is not active.
Reading 1 from this bit implies that the interrupt line 20 is active (See
EVENT:CPUIRQSEL20.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 19 is not active.
Reading 1 from this bit implies that the interrupt line 19 is active (See
EVENT:CPUIRQSEL19.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 18 is not active.
Reading 1 from this bit implies that the interrupt line 18 is active (See
EVENT:CPUIRQSEL18.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 17 is not active.
Reading 1 from this bit implies that the interrupt line 17 is active (See
EVENT:CPUIRQSEL17.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 16 is not active.
Reading 1 from this bit implies that the interrupt line 16 is active (See
EVENT:CPUIRQSEL16.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 15 is not active.
Reading 1 from this bit implies that the interrupt line 15 is active (See
EVENT:CPUIRQSEL15.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 14 is not active.
Reading 1 from this bit implies that the interrupt line 14 is active (See
EVENT:CPUIRQSEL14.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 13 is not active.
Reading 1 from this bit implies that the interrupt line 13 is active (See
EVENT:CPUIRQSEL13.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 12 is not active.
Reading 1 from this bit implies that the interrupt line 12 is active (See
EVENT:CPUIRQSEL12.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 11 is not active.
Reading 1 from this bit implies that the interrupt line 11 is active (See
EVENT:CPUIRQSEL11.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 10 is not active.
Reading 1 from this bit implies that the interrupt line 10 is active (See
EVENT:CPUIRQSEL10.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 9 is not active.
Reading 1 from this bit implies that the interrupt line 9 is active (See
EVENT:CPUIRQSEL9.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 8 is not active.
Reading 1 from this bit implies that the interrupt line 8 is active (See
EVENT:CPUIRQSEL8.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 7 is not active.
Reading 1 from this bit implies that the interrupt line 7 is active (See
EVENT:CPUIRQSEL7.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 6 is not active.
Reading 1 from this bit implies that the interrupt line 6 is active (See
EVENT:CPUIRQSEL6.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 5 is not active.
Reading 1 from this bit implies that the interrupt line 5 is active (See
EVENT:CPUIRQSEL5.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 4 is not active.
Reading 1 from this bit implies that the interrupt line 4 is active (See
EVENT:CPUIRQSEL4.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 3 is not active.
Reading 1 from this bit implies that the interrupt line 3 is active (See
EVENT:CPUIRQSEL3.EV for details).
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Cortex-M3 Processor Registers
153