Texas Instruments SimpleLink CC2620 Technical Reference Manual page 38

Cortex-M3 Core Registers
2.5.2.11 Cortex General-Purpose Register 10 (R10)
Address Offset
Physical Address
Description
Type
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits Field Name
31–0 DATA
2.5.2.12 Cortex General-Purpose Register 11 (R11)
Address Offset
Physical Address
Description
Type
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits Field Name
31–0 DATA
2.5.2.13 Cortex General-Purpose Register 12 (R12)
Address Offset
Physical Address
Description
Type
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits Field Name
31–0 DATA
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Table 2-13. Cortex General-Purpose Register 10 (R10)
The R10 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
R/W
Description
Register data
Table 2-14. Cortex General-Purpose Register 11 (R11)
The R11 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
R/W
Description
Register data
Table 2-15. Cortex General-Purpose Register 12 (R12)
The R12 registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.
R/W
Description
Register data
Copyright © 2015, Texas Instruments Incorporated
Reset
Instance
9
DATA
Reset
Instance
9
DATA
Reset
Instance
9
DATA
SWCU117C – February 2015 – Revised September 2015
www.ti.com
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8 7 6 5 4 3 2 1
Type Reset
R/W —
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8 7 6 5 4 3 2 1
Type Reset
R/W —
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8 7 6 5 4 3 2 1
Type Reset
R/W —
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