Texas Instruments SimpleLink CC2620 Technical Reference Manual page 172

Cortex-M3 Processor Registers
Bit Field
1 USERSETMPEND
0 NONBASETHREDENA
172
Table 2-127. CCR Register Field Descriptions (continued)
Type Reset
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Description
Enables unprivileged software access to STIR:
0: User code is not allowed to write to the Software Trigger Interrupt
register (STIR).
1: User code can write the Software Trigger Interrupt register (STIR)
to trigger (pend) a Main exception, which is associated with the Main
stack pointer.
Indicates how the processor enters Thread mode:
0: Processor can enter Thread mode only when no exception is
active.
1: Processor can enter Thread mode from any level using the
appropriate return value (EXC_RETURN).
Exception returns occur when one of the following instructions loads
a value of 0xFXXXXXXX into the PC while in Handler mode:
- POP/LDM which includes loading the PC.
- LDR with PC as a destination.
- BX with any register.
The value written to the PC is intercepted and is referred to as the
EXC_RETURN value.
SWCU117C – February 2015 – Revised September 2015
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