Texas Instruments SimpleLink CC2620 Technical Reference Manual page 140

Cortex-M3 Processor Registers
2.7.4.9 NVIC_ICER0 Register (Offset = 180h) [reset = 0h]
NVIC_ICER0 is shown in
Irq 0 to 31 Clear Enable
This register is used to disable interrupts and determine which interrupts are currently enabled.
31 30
CLRENA31 CLRENA30
R/W-0h R/W-0h
23 22
CLRENA23 CLRENA22
R/W-0h R/W-0h
15 14
CLRENA15 CLRENA14
R/W-0h R/W-0h
7 6
CLRENA7 CLRENA6
R/W-0h R/W-0h
Bit Field
31 CLRENA31
30 CLRENA30
29 CLRENA29
28 CLRENA28
27 CLRENA27
26 CLRENA26
25 CLRENA25
24 CLRENA24
23 CLRENA23
22 CLRENA22
21 CLRENA21
140
Figure 2-79 and described in
Figure 2-79. NVIC_ICER0 Register
29 28
CLRENA29 CLRENA28
R/W-0h R/W-0h
21 20
CLRENA21 CLRENA20
R/W-0h R/W-0h
13 12
CLRENA13 CLRENA12
R/W-0h R/W-0h
5 4
CLRENA5 CLRENA4
R/W-0h R/W-0h
Table 2-105. NVIC_ICER0 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-105.
27 26
CLRENA27 CLRENA26
R/W-0h R/W-0h
19 18
CLRENA19 CLRENA18
R/W-0h R/W-0h
11 10
CLRENA11 CLRENA10
R/W-0h R/W-0h
3 2
CLRENA3 CLRENA2
R/W-0h R/W-0h
Description
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current enable state.
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current enable state.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
CLRENA25 CLRENA24
R/W-0h R/W-0h
17 16
CLRENA17 CLRENA16
R/W-0h R/W-0h
9 8
CLRENA9 CLRENA8
R/W-0h R/W-0h
1 0
CLRENA1 CLRENA0
R/W-0h R/W-0h
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