Module Description - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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If the AHB_MST1_LOCK_EN bit is asserted, the AHB master asserts a lock signal to indicate the AHB is
performing a number of indivisible transfers. The arbiter does not grant any other AHB master access to
the bus when the first transfer of the sequence of locked transfers has commenced. The AHB master
inserts an IDLE transfer after each block sequence.
The AHB master can handle big- and little-endian transfers. The AES module is little endian-oriented
internally. However, when connected to a big-endian AHB system, a conversion from big to little endian
can be done in the AHB master interface. By default, a little endian-oriented AHB-host system is assumed.
When the AHB system is big endian-oriented, the AHB_MST1_BIGEND bit must be set to 1.
NOTE: The CC26xx and CC13xx devices do not support burst or nonsequential transfers through
internal interconnect. The DMABUSCFG register must not be changed for proper operation.
10.1.3.3 Interrupts
The AES module has two interrupt outputs; both are driven from the master control module and are
controlled by the respective registers (see
To enable interrupts for the AES engine, thr IRQTYPE.EN bit must be set and the interrupt source must
be configured in the IRQEN register.
The IRQCLR register is available to clear an interrupt output and error-status bit. The IRQSET register
provides the software a way to test the interrupt connections and must be used for debugging only.
The IRQSTAT register provides the status of the two interrupts along with error status messages. The
error status bits are asserted once they are detected, and typically the value of DMA_BUS_ERR and
KEY_ST_WR_ERR signals are valid after the RESULT_AVAIL bit is asserted. The KEY_ST_RD_ERR bit
is valid after triggering the key store module to read a key from memory and providing it to the AES
engine.
An interrupt RESULT_AVAIL is activated when an operation that uses DMA is finished. The signal asserts
when both the DMA and internal module are in the idle state.
Another interrupt DMA_IN_DONE is activated when only the input DMA is finished and is intended for
debugging.
NOTE: Interrupt outputs are not triggered for operations where the DMA is not used.

10.1.4 Module Description

10.1.4.1 Introduction
This section describes some accessible registers, internal interfaces, and module functionality. The
registers and functionality are discussed for each submodule. For complete information on the module
registers, see Section
10.1.4.2 Module Memory Map
Physical Address Register Name
DMA Controller Registers
0x4002 4000 DMACH0CTL
0x4002 4004 DMACH0EXTADDR
0x4002 400C DMACH0LEN
0x4002 4018 DMASTAT
SWCU117C – February 2015 – Revised September 2015
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Section
10.2.1, CRYPTO Registers.
Table 10-1. Detailed Memory Map
Type
R/W
R/W
R/W
R
Copyright © 2015, Texas Instruments Incorporated
10.1.4.4.3, Software Reset).
Reset Value Remark
0x0000 0000 Channel 0 control
register
0x0000 0000 Channel 0 external
address
0x0000 0000 Channel 0 DMA
length
0x0000 0000 DMAC status
AES Cryptoprocessor Overview
Link
Section 10.2.1.1
Section 10.2.1.2
Section 10.2.1.3
Section 10.2.1.4
Cryptography
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