Texas Instruments SimpleLink CC2620 Technical Reference Manual page 192

Cortex-M3 Processor Registers
2.7.4.49 ID_MMFR3 Register (Offset = D5Ch) [reset = 0h]
ID_MMFR3 is shown in
Memory Model Feature 3
General information on the memory model and memory management support.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 RESERVED
192
Figure 2-119 and described in
Figure 2-119. ID_MMFR3 Register
RESERVED
R-0h
Table 2-145. ID_MMFR3 Register Field Descriptions
Type Reset
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-145.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
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