Texas Instruments SimpleLink CC2620 Technical Reference Manual page 465

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6.2.3.8 CTL0 Register (Offset = 20h) [reset = 0h]
CTL0 is shown in Figure 6-33
Control 0
This register contains various chip level control and debug bitfields.
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-9 RESERVED
8 PWR_DWN_DIS
7-4 RESERVED
3 AUX_SRAM_ERASE
2 MCU_SRAM_ERASE
1-0 RESERVED
SWCU117C – February 2015 – Revised September 2015
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and described in
Figure 6-33. CTL0 Register
29 28
21 20
13 12
RESERVED
R-0h
5 4
R/W-0h
Table 6-37. CTL0 Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
W 0h
W 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-37.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
3
AUX_SRAM_E MCU_SRAM_E
RASE RASE
W-0h W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Controls whether MCU and AUX requesting to be powered off will
enable a transition to powerdown:
0: Enabled
1: Disabled
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Power, Reset, and Clock Management
PRCM Registers
26 25
18 17
10 9
PWR_DWN_DI
2 1
RESERVED
R-0h
24
16
8
S
R/W-0h
0
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