Texas Instruments SimpleLink CC2620 Technical Reference Manual page 151

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2.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [reset = 0h]
NVIC_ICPR1 is shown in
Irq 32 to 63 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.
31 30
23 22
15 14
7 6
Bit Field
31-2 RESERVED
1 CLRPEND33
0 CLRPEND32
SWCU117C – February 2015 – Revised September 2015
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Figure 2-84 and described in
Figure 2-84. NVIC_ICPR1 Register
29 28
RESERVED
R/W-0h
21 20
RESERVED
R/W-0h
13 12
RESERVED
R/W-0h
5 4
RESERVED
R/W-0h
Table 2-110. NVIC_ICPR1 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-110.
27 26
19 18
11 10
3 2
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV
for details). Reading the bit returns its current state.
Cortex-M3 Processor Registers
25 24
17 16
9 8
1 0
CLRPEND33 CLRPEND32
R/W-0h R/W-0h
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