Exception Handlers - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Exception Model
• Bus Fault: A bus fault is an exception that occurs because of a memory-related fault for an instruction
or data memory transaction such as a prefetch fault or a memory access fault. This fault can be
enabled or disabled.
• Usage Fault: A usage fault is an exception that occurs because of a fault related to instruction
execution, such as the following:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
– An error on exception return
An unaligned address on a word or halfword memory access or division by 0 can cause a usage fault
when the core is properly configured.
• SVCall: A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS
environment, applications can use SVC instructions to access OS kernel functions and device drivers.
• Debug Monitor: This exception is caused by the debug monitor (when not halting). This exception is
active only when enabled. This exception does not activate if it is a lower priority than the current
activation.
• PendSV: PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is triggered
using the Interrupt Control and State CPU_SCS:ICSR register.
• SysTick: A SysTick exception is generated by the system timer when it reaches 0 and is enabled to
generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and
State register, CPU_SCS:ICSR. In an OS environment, the processor can use this exception as
system tick.
• Interrupt (IRQ): An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a
software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction
execution. In the system, peripherals use interrupts to communicate with the processor.
the interrupts on the CC26xx and CC13xx controller.
For an asynchronous exception, other than reset, the processor can execute another instruction between
when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that
the CPU_SCS:SHCSR register in
CPU_SCS:NVIC_ICER0 register in
For more information about hard faults, bus faults, and usage faults, see
Exception Type
–
Reset
–
Hard fault
Bus fault
Usage fault
–
SVCall
Debug monitor
(1)
0 is the default priority for all the programmable priorities.
(2)
See Section 4.1.4.
(3)
See CPU_SCS:SHPR 1 in
230 Interrupts and Events
Section 2.7.4.35, SHCSR Register (Offset = D24h) [reset = X] and the
Section 2.7.4.9, NVIC_ICER0 Register (Offset = 180h) [reset = X]).
Table 4-1. Exception Types
Vector Number Priority
0
1 –3 (highest)
–
3
5 Programmable
6 Programmable
7 to 10
11 Programmable
12 Programmable
Figure 2-102, SHPR1 Register (Offset = D18h) [reset = X].
Copyright © 2015, Texas Instruments Incorporated
Table 4-1 shows as having configurable priority(see
Section
Vector Address or
(1)
(2)
Offset
– 0x0000 0000
0x0000 0004
– –
–1 0x0000 000C
(3)
0x0000 0014
0x0000 0018
– –
0x0000 002C
0x0000 0030
SWCU117C – February 2015 – Revised September 2015
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Table 4-8 lists
4.2, Fault Handling.
Activation
Stack top is loaded from
the first entry of the
vector table on reset.
Asynchronous
–
–
Synchronous when
precise and
asynchronous when
imprecise
Synchronous
Reserved
Synchronous
Synchronous
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