Texas Instruments SimpleLink CC2620 Technical Reference Manual page 161

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2.7.4.22 NVIC_IPR5 Register (Offset = 414h) [reset = 0h]
NVIC_IPR5 is shown in
Irq 20 to 23 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest
priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the
setting in AIRCR.PRIGROUP.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_23
R/W-0h
Bit Field
31-24 PRI_23
23-16 PRI_22
15-8 PRI_21
7-0 PRI_20
SWCU117C – February 2015 – Revised September 2015
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Figure 2-92 and described in
Figure 2-92. NVIC_IPR5 Register
PRI_22
R/W-0h
Table 2-118. NVIC_IPR5 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-118.
9
PRI_21
R/W-0h
Description
Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details).
Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details).
Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details).
Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details).
Cortex-M3 Processor Registers
8 7 6 5 4 3 2 1
PRI_20
R/W-0h
0
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