Texas Instruments SimpleLink CC2620 Technical Reference Manual page 148

Cortex-M3 Processor Registers
2.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [reset = 0h]
NVIC_ICPR0 is shown in
Irq 0 to 31 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.
31 30
CLRPEND31 CLRPEND30
R/W-0h R/W-0h
23 22
CLRPEND23 CLRPEND22
R/W-0h R/W-0h
15 14
CLRPEND15 CLRPEND14
R/W-0h R/W-0h
7 6
CLRPEND7 CLRPEND6
R/W-0h R/W-0h
Bit Field
31 CLRPEND31
30 CLRPEND30
29 CLRPEND29
28 CLRPEND28
27 CLRPEND27
26 CLRPEND26
25 CLRPEND25
24 CLRPEND24
23 CLRPEND23
22 CLRPEND22
21 CLRPEND21
148
Figure 2-83 and described in
Figure 2-83. NVIC_ICPR0 Register
29 28
CLRPEND29 CLRPEND28
R/W-0h R/W-0h
21 20
CLRPEND21 CLRPEND20
R/W-0h R/W-0h
13 12
CLRPEND13 CLRPEND12
R/W-0h R/W-0h
5 4
CLRPEND5 CLRPEND4
R/W-0h R/W-0h
Table 2-109. NVIC_ICPR0 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-109.
27 26
CLRPEND27 CLRPEND26
R/W-0h R/W-0h
19 18
CLRPEND19 CLRPEND18
R/W-0h R/W-0h
11 10
CLRPEND11 CLRPEND10
R/W-0h R/W-0h
3 2
CLRPEND3 CLRPEND2
R/W-0h R/W-0h
Description
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV
for details). Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV
for details). Reading the bit returns its current state.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
CLRPEND25 CLRPEND24
R/W-0h R/W-0h
17 16
CLRPEND17 CLRPEND16
R/W-0h R/W-0h
9 8
CLRPEND9 CLRPEND8
R/W-0h R/W-0h
1 0
CLRPEND1 CLRPEND0
R/W-0h R/W-0h
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