Texas Instruments SimpleLink CC2620 Technical Reference Manual page 726

Factory Configuration (FCFG)
9.2.1.7 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = FFFFFFFFh]
CONFIG_RF_FRONTEND_DIV30 is shown in
Configuration of RF Frontend in Divide-by-30 Mode
Divide-by-30 mode is only available for CC13xx.
31 30 29 28
IFAMP_IB
R-Fh
15 14 13 12
CTL_PA0_TRI
M
R-1Fh
Table 9-31. CONFIG_RF_FRONTEND_DIV30 Register Field Descriptions
Bit Field
31-28 IFAMP_IB
27-24 LNA_IB
23-19 IFAMP_TRIM
18-14 CTL_PA0_TRIM
13-7 RESERVED
6-0 RFLDO_TRIM_OUTPUT
726
Device Configuration
Figure 9-29
Figure 9-29. CONFIG_RF_FRONTEND_DIV30 Register
27 26 25 24
LNA_IB
R-Fh
11 10 9 8
RESERVED
R-7Fh
Type Reset
R Fh
R Fh
R 1Fh
R 1Fh
R 7Fh
R 7Fh
Copyright © 2015, Texas Instruments Incorporated
and described in
23 22 21 20
IFAMP_TRIM
R-1Fh
7 6 5 4
RFLDO_TRIM_OUTPUT
Description
Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.
Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.
Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.
Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
Table 9-31.
19 18 17
CTL_PA0_TRIM
R-1Fh
3 2 1
R-7Fh
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