Texas Instruments SimpleLink CC2620 Technical Reference Manual page 212

Cortex-M3 Processor Registers
2.7.5.5 FFSR Register (Offset = 300h) [reset = 8h]
FFSR is shown in
Formatter and Flush Status
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3 FTNONSTOP
2-0 RESERVED
212
Figure 2-135 and described in
Figure 2-135. FFSR Register
29 28
21 20
13 12
5 4
R-0h
Table 2-162. FFSR Register Field Descriptions
Type Reset
R 0h
R 1h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-162.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
FTNONSTOP
R-1h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0: Formatter can be stopped
1: Formatter cannot be stopped
This field always reads as zero
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
RESERVED
R-0h
Submit Documentation Feedback
www.ti.com
24
16
8
0