Texas Instruments SimpleLink CC2620 Technical Reference Manual page 521

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6.2.4.46 PDCTL1 Register (Offset = 17Ch) [reset = Ah]
PDCTL1 is shown in
Power Domain Control
31 30
23 22
15 14
7 6
RESERVED
R-0h
Bit Field
31-5 RESERVED
4 RESERVED
3 VIMS_MODE
2 RFC_ON
1 CPU_ON
0 RESERVED
SWCU117C – February 2015 – Revised September 2015
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Figure 6-85 and described in
Figure 6-85. PDCTL1 Register
29 28
RESERVED
21 20
RESERVED
13 12
RESERVED
5 4
RESERVED
R/W-0h
Table 6-90. PDCTL1 Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 1h
R/W 0h
R/W 1h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-90.
27 26
R-0h
19 18
R-0h
11 10
R-0h
3 2
VIMS_MODE RFC_ON
R/W-1h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0: VIMS power domain is only powered when CPU power domain is
powered.
1: VIMS power domain is powered whenever the BUS power domain
is powered.
0: RFC power domain powered off if also PDCTL0.RFC_ON = 0
1: RFC power domain powered on
Bit shall be used by RFC in autonomus mode but there is no HW
restrictions fom system CPU to access the bit.
0: Causes a power down of the CPU power domain when system
CPU indicates it is idle.
1: Initiates power-on of the CPU power domain.
This bit is automatically set by a WIC power-on event.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Power, Reset, and Clock Management
PRCM Registers
25 24
17 16
9 8
1 0
CPU_ON RESERVED
R/W-1h R-0h
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