Texas Instruments SimpleLink CC2620 Technical Reference Manual page 57

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2.7.1.5 SLEEPCNT Register (Offset = 10h) [reset = X]
SLEEPCNT is shown in
Sleep Count
This register is used to count the total number of cycles during which the processor is sleeping.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-8 RESERVED
7-0 SLEEPCNT
SWCU117C – February 2015 – Revised September 2015
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Figure 2-8 and described in
Figure 2-8. SLEEPCNT Register
RESERVED
R/W-0h
Table 2-31. SLEEPCNT Register Field Descriptions
Type Reset
R/W 0h
R/W X
Copyright © 2015, Texas Instruments Incorporated
Table 2-31.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Sleep counter. Counts the number of cycles during which the
processor is sleeping. An event is emitted on counter overflow (every
256 cycles). This counter initializes to 0 when it is enabled using
CTRL.SLEEPEVTENA. Note that the sleep counter is clocked using
CPU's free-running clock. In some power modes the free-running
clock to CPU is gated to minimize power consumption. This means
that the sleep counter will be invalid in these power modes.
Cortex-M3 Processor Registers
8 7 6 5 4 3 2 1
SLEEPCNT
R/W-X
0
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