Texas Instruments SimpleLink CC2620 Technical Reference Manual page 169

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2.7.4.29 AIRCR Register (Offset = D0Ch) [reset = FA050000h]
AIRCR is shown in
Application Interrupt/Reset Control
This register is used to determine data endianness, clear all active state information for debug or to
recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).
31 30
23 22
15 14
ENDIANESS
R-0h
7 6
Bit Field
31-16 VECTKEY
15 ENDIANESS
14-11 RESERVED
10-8 PRIGROUP
7-3 RESERVED
2 SYSRESETREQ
1 VECTCLRACTIVE
0 VECTRESET
SWCU117C – February 2015 – Revised September 2015
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Figure 2-99 and described in
Figure 2-99. AIRCR Register
29 28
21 20
13 12
RESERVED
R-0h
5 4
RESERVED
R/W-0h
Table 2-125. AIRCR Register Field Descriptions
Type Reset
R/W FA05h
R 0h
R 0h
R/W 0h
R/W 0h
W 0h
W 0h
W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-125.
27
VECTKEY
R/W-FA05h
19
VECTKEY
R/W-FA05h
11
3
SYSRESETRE VECTCLRACTI
W-0h
Description
Register key. Writing to this register (AIRCR) requires 0x05FA in
VECTKEY. Otherwise the write value is ignored. Read always
returns 0xFA05.
Data endianness bit
0h = Little endian
1h = Big endian
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Interrupt priority grouping field. This field is a binary point position
indicator for creating subpriorities for exceptions that share the same
pre-emption level. It divides the PRI_n field in the Interrupt Priority
Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-
emption level and a subpriority level. The binary point is a left-of
value. This means that the PRIGROUP value represents a point
starting at the left of the Least Significant Bit (LSB). The lowest value
might not be 0 depending on the number of bits allocated for
priorities, and implementation choices.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Requests a warm reset. Setting this bit does not prevent Halting
Debug from running.
Clears all active state information for active NMI, fault, and
interrupts. It is the responsibility of the application to reinitialize the
stack. This bit is for returning to a known state during debug. The bit
self-clears. IPSR is not cleared by this operation. So, if used by an
application, it must only be used at the base level of activation, or
within a system handler whose active bit can be set.
System Reset bit. Resets the system, with the exception of debug
components. This bit is reserved for debug use and can be written to
1 only when the core is halted. The bit self-clears. Writing this bit to
1 while core is not halted may result in unpredictable behavior.
Cortex-M3 Processor Registers
26 25
18 17
10 9
PRIGROUP
R/W-0h
2 1
VECTRESET
Q VE
W-0h
24
16
8
0
W-0h
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