Texas Instruments SimpleLink CC2620 Technical Reference Manual page 528

PRCM Registers
6.2.4.53 PDSTAT1CPU Register (Offset = 1A0h) [reset = 1h]
PDSTAT1CPU is shown in
CPU Power Domain Status
31 30 29 28
15 14 13 12
Bit Field
31-1 RESERVED
0 ON
528
Power, Reset, and Clock Management
Figure 6-92 and described in
Figure 6-92. PDSTAT1CPU Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-97. PDSTAT1CPU Register Field Descriptions
Type Reset
R 0h
R 1h
Copyright © 2015, Texas Instruments Incorporated
Table 6-97.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
This is an alias for PDSTAT1.CPU_ON
SWCU117C – February 2015 – Revised September 2015
www.ti.com
19 18 17 16
3 2 1 0
ON
R-1h
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