Texas Instruments SimpleLink CC2620 Technical Reference Manual page 180

Zigbee rf4ce wireless mcu simplelink cc13 series; simplelink cc26 series

Cortex-M3 Processor Registers

2.7.4.37 HFSR Register (Offset = D2Ch) [reset = 0h]

HFSR is shown in

Hard Fault Status

This register is used to obtain information about events that activate the Hard Fault handler. This register

is a write-clear register. This means that writing a 1 to a bit clears that bit.

Figure 2-107

and described in

Figure 2-107. HFSR Register

Table 2-133. HFSR Register Field Descriptions

This bit is set if there is a fault related to debug. This is only possible

when halting debug is not enabled. For monitor enabled debug, it

only happens for BKPT when the current priority is higher than the

monitor. When both halting and monitor debug are disabled, it only

happens for debug events that are not ignored (minimally, BKPT).

The Debug Fault Status Register is updated.

Hard Fault activated because a Configurable Fault was received and

cannot activate because of priority or because the Configurable Fault

is disabled. The Hard Fault handler then has to read the other fault

status registers to determine cause.

Software must not rely on the value of a reserved. Writing any other

value than the reset value may result in undefined behavior.

This bit is set if there is a fault because of vector table read on

exception processing (Bus Fault). This case is always a Hard Fault.

The return PC points to the pre-empted instruction.

Software must not rely on the value of a reserved. Writing any other

value than the reset value may result in undefined behavior.

SWCU117C – February 2015 – Revised September 2015

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