Texas Instruments SimpleLink CC2620 Technical Reference Manual page 271

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Offset Acronym
200h GPT0ACAPTSEL
204h GPT0BCAPTSEL
300h GPT1ACAPTSEL
304h GPT1BCAPTSEL
400h GPT2ACAPTSEL
404h GPT2BCAPTSEL
508h UDMACH1SSEL
50Ch UDMACH1BSEL
510h UDMACH2SSEL
514h UDMACH2BSEL
518h UDMACH3SSEL
51Ch UDMACH3BSEL
520h UDMACH4SSEL
524h UDMACH4BSEL
528h UDMACH5SSEL
52Ch UDMACH5BSEL
530h UDMACH6SSEL
534h UDMACH6BSEL
538h UDMACH7SSEL
53Ch UDMACH7BSEL
540h UDMACH8SSEL
544h UDMACH8BSEL
548h UDMACH9SSEL
54Ch UDMACH9BSEL
550h UDMACH10SSEL
554h UDMACH10BSEL
558h UDMACH11SSEL
55Ch UDMACH11BSEL
560h UDMACH12SSEL
564h UDMACH12BSEL
56Ch UDMACH13BSEL
574h UDMACH14BSEL
57Ch UDMACH15BSEL
580h UDMACH16SSEL
584h UDMACH16BSEL
588h UDMACH17SSEL
58Ch UDMACH17BSEL
5A8h UDMACH21SSEL
5ACh UDMACH21BSEL
5B0h UDMACH22SSEL
5B4h UDMACH22BSEL
5B8h UDMACH23SSEL
5BCh UDMACH23BSEL
5C0h UDMACH24SSEL
5C4h UDMACH24BSEL
600h GPT3ACAPTSEL
604h GPT3BCAPTSEL
SWCU117C – February 2015 – Revised September 2015
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Table 4-14. EVENT Registers (continued)
Register Name
Output Selection for GPT0 0
Output Selection for GPT0 1
Output Selection for GPT1 0
Output Selection for GPT1 1
Output Selection for GPT2 0
Output Selection for GPT2 1
Output Selection for DMA Channel 1 SREQ
Output Selection for DMA Channel 1 REQ
Output Selection for DMA Channel 2 SREQ
Output Selection for DMA Channel 2 REQ
Output Selection for DMA Channel 3 SREQ
Output Selection for DMA Channel 3 REQ
Output Selection for DMA Channel 4 SREQ
Output Selection for DMA Channel 4 REQ
Output Selection for DMA Channel 5 SREQ
Output Selection for DMA Channel 5 REQ
Output Selection for DMA Channel 6 SREQ
Output Selection for DMA Channel 6 REQ
Output Selection for DMA Channel 7 SREQ
Output Selection for DMA Channel 7 REQ
Output Selection for DMA Channel 8 SREQ
Output Selection for DMA Channel 8 REQ
Output Selection for DMA Channel 9 SREQ
Output Selection for DMA Channel 9 REQ
Output Selection for DMA Channel 10 SREQ
Output Selection for DMA Channel 10 REQ
Output Selection for DMA Channel 11 SREQ
Output Selection for DMA Channel 11 REQ
Output Selection for DMA Channel 12 SREQ
Output Selection for DMA Channel 12 REQ
Output Selection for DMA Channel 13 REQ
Output Selection for DMA Channel 14 REQ
Output Selection for DMA Channel 15 REQ
Output Selection for DMA Channel 16 SREQ
Output Selection for DMA Channel 16 REQ
Output Selection for DMA Channel 17 SREQ
Output Selection for DMA Channel 17 REQ
Output Selection for DMA Channel 21 SREQ
Output Selection for DMA Channel 21 REQ
Output Selection for DMA Channel 22 SREQ
Output Selection for DMA Channel 22 REQ
Output Selection for DMA Channel 23 SREQ
Output Selection for DMA Channel 23 REQ
Output Selection for DMA Channel 24 SREQ
Output Selection for DMA Channel 24 REQ
Output Selection for GPT3 0
Output Selection for GPT3 1
Copyright © 2015, Texas Instruments Incorporated
Interrupts and Events Registers
Section
Section 4.7.2.45
Section 4.7.2.46
Section 4.7.2.47
Section 4.7.2.48
Section 4.7.2.49
Section 4.7.2.50
Section 4.7.2.51
Section 4.7.2.52
Section 4.7.2.53
Section 4.7.2.54
Section 4.7.2.55
Section 4.7.2.56
Section 4.7.2.57
Section 4.7.2.58
Section 4.7.2.59
Section 4.7.2.60
Section 4.7.2.61
Section 4.7.2.62
Section 4.7.2.63
Section 4.7.2.64
Section 4.7.2.65
Section 4.7.2.66
Section 4.7.2.67
Section 4.7.2.68
Section 4.7.2.69
Section 4.7.2.70
Section 4.7.2.71
Section 4.7.2.72
Section 4.7.2.73
Section 4.7.2.74
Section 4.7.2.75
Section 4.7.2.76
Section 4.7.2.77
Section 4.7.2.78
Section 4.7.2.79
Section 4.7.2.80
Section 4.7.2.81
Section 4.7.2.82
Section 4.7.2.83
Section 4.7.2.84
Section 4.7.2.85
Section 4.7.2.86
Section 4.7.2.87
Section 4.7.2.88
Section 4.7.2.89
Section 4.7.2.90
Section 4.7.2.91
Interrupts and Events
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