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7.8.1.111 FSM_BSLP1 Register (Offset = 22F4h) [reset = 0h]
FSM_BSLP1 is shown in
Internal. Only to be used through TI provided API.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Field
31-0
FSM_BSL1
SWCU117C – February 2015 – Revised September 2015
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Figure 7-120
and described in
Figure 7-120. FSM_BSLP1 Register
FSM_BSL1
R/W-0h
Table 7-114. FSM_BSLP1 Register Field Descriptions
Type
Reset
R/W
0h
Copyright © 2015, Texas Instruments Incorporated
Table
7-114.
9
Description
Internal. Only to be used through TI provided API.
Versatile Instruction Memory System (VIMS)
VIMS Registers
8
7
6
5
4
3
2
1
0
657