Texas Instruments SimpleLink CC2620 Technical Reference Manual page 825

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10.1.6.4 Exceptions Handling
10.1.6.4.1 Soft Reset
If required, the AES module can be forced to abort its current active operation and go into idle state using
the soft reset.
The idle state means the following:
• The DMAC is not actively performing DMA operations.
• The cryptographic modules are in idle state.
• The key store module does not have any keys loaded.
• The master control module is in idle state.
• A soft reset must be executed in the following order:
– If DMA is used and in operation, it must be stopped.
– The master control module must be reset through the SWRESET register.
• Write the mode and length registers for the crypto core with zeroes.
The mode and length registers are:
– AESCTL
– AESDATALEN0
– AESDATALEN1
– AESAUTHLEN
10.1.6.4.2 External Port Errors
The AHB master interface and the DMAC inside the crypto core can detect AHB port errors received
through the AHB_ERR signal.
In this situation, the DMAC disables all channels so that no new transfers are requested, while the error is
captured in the status registers. The DMAPORTERR register contains information about the active
channel when the AHB port error occurred. The DMAC indicates the channel completion to the master
control module. The recovery procedure is as follows:
• Issue a soft reset to the DMAC using the DMASWRESET register to clear the DMAPORTERR register
and initialize the channels to their default state
• Issue a soft reset to the master control module to clear its intermediate state.
10.1.6.4.3 Key Store Errors
Key store error generation is implemented for debugging purposes. In normal or specified operation, the
crypto core key store writes and reads must not trigger any errors. A bus error is the only exceptional case
that can result in a key store write error.
The key store module checks that the keys are properly written to the key store RAM. When a key write
error occurs, the KEY_ST_WR_ERR flag is asserted in the IRQSTAT register. In this case, the key is not
stored. The host must check the status of the KEY_ST_WR_ERR flag and ensure that the corresponding
RAM area is not used for AES operations.
If, due to software malfunction, the host tries to use a key from a nonwritten RAM area, the key store
module generates a read error. In this case, the KEY_ST_RD_ERR flag is asserted in the IRQSTAT
register. The host must check the status of this flag and ensure that all remaining steps for the AES
operation are not performed.
NOTE: In case of a read error, the key store writes a key with all bytes set to 0 to the AES engine.
SWCU117C – February 2015 – Revised September 2015
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AES Cryptoprocessor Overview
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