Texas Instruments SimpleLink CC2620 Technical Reference Manual page 778

Factory Configuration (FCFG)
9.2.1.57 CONFIG_SYNTH Register (Offset = 358h) [reset = X]
CONFIG_SYNTH is shown in
Configuration of Synthesizer in Divide-by-2 Mode
31 30 29 28
RESERVED
R-Fh
15 14 13 12
RFC_MDM_DEMIQMC0
R-FFFFh
Bit Field
31-28 RESERVED
27-12 RFC_MDM_DEMIQMC0
11-6 LDOVCO_TRIM_OUTPU
T
5-0 SLDO_TRIM_OUTPUT
778
Device Configuration
Figure 9-79 and described in
Figure 9-79. CONFIG_SYNTH Register
27 26 25 24
11 10 9 8
LDOVCO_TRIM_OUTPUT
R-X
Table 9-81. CONFIG_SYNTH Register Field Descriptions
Type Reset
R Fh
R FFFFh
R X
R X
Copyright © 2015, Texas Instruments Incorporated
Table 9-81.
23 22 21 20
RFC_MDM_DEMIQMC0
R-FFFFh
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and
RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization only
on cc13xx.
Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.
Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
19 18 17
3 2 1
SLDO_TRIM_OUTPUT
R-X
Submit Documentation Feedback
16
0