Texas Instruments SimpleLink CC2620 Technical Reference Manual page 505

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6.2.4.30 I2SBCLKSEL Register (Offset = C8h) [reset = 0h]
I2SBCLKSEL is shown in
I2S Clock Control
31 30 29 28
15 14 13 12
Bit Field
31-1 SPARE
0 SRC
SWCU117C – February 2015 – Revised September 2015
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Figure 6-69 and described in
Figure 6-69. I2SBCLKSEL Register
27 26 25 24
SPARE
R/W-0h
11 10 9 8
SPARE
R/W-0h
Table 6-74. I2SBCLKSEL Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-74.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
BCLK source selector
0: Use external BCLK
1: Use internally generated clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Power, Reset, and Clock Management
PRCM Registers
19 18 17 16
3 2 1 0
SRC
R/W-
0h
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