Texas Instruments SimpleLink CC2620 Technical Reference Manual page 829

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10.2.1.1 DMACH0CTL Register (Offset = 0h) [reset = 0h]
DMACH0CTL is shown in
DMA Channel 0 Control
31 30
23 22
15 14
7 6
Bit Field
31-2 RESERVED
1 PRIO
0 EN
SWCU117C – February 2015 – Revised September 2015
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Figure 10-3 and described in
Figure 10-3. DMACH0CTL Register
29 28
RESERVED
R/W-0h
21 20
RESERVED
R/W-0h
13 12
RESERVED
R/W-0h
5 4
RESERVED
R/W-0h
Table 10-11. DMACH0CTL Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 10-11.
27 26
19 18
11 10
3 2
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Channel priority:
A channel with high priority will be served before a channel with low
priority in cases with simultaneous access requests. If both channels
have the same priority access of the channels to the external port is
arbitrated using a Round Robin scheme.
0h = Priority low
1h = Priority high
DMA Channel 0 Control
0h = Channel disabled
1h = Channel enabled
Cryptography Registers
25 24
17 16
9 8
1 0
PRIO EN
R/W-0h R/W-0h
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