Texas Instruments SimpleLink CC2620 Technical Reference Manual page 399

www.ti.com
Number Test TAP Name
Test Banks
0 TEST
1 PBIST1.0
2 PBIST2.0
3 eFuse
4 PRCM
5 AON WUC
Debug Banks
0 CM3
(1)
The test TAP is locked for all devices except CC2650. This TAP implements a profiler register that can be used to extract runtime
information about program execution and general chip status. The access to this TAP can be blocked by writing to the corresponding
field in the customer configuration area (see
(2)
Some of the registers in AON WUC TAP are open for end user. This includes registers for requesting chip erase, system reset, and MCU
reset.
(3)
The access to debug port of the CPU can be blocked by writing to corresponding field in customer configuration area (see
5.3.1.1 Slave DAP (CPU DAP)
The debug subsystem has only one slave DAP (CPU DAP). This debug port implements Serial Wire JTAG
Debug Port (SWJ-DP) interface, which allows external access to an Advanced High-performance Bus
Access Port (AHB-AP) interface for debug accesses in the CPU.
The SWJ-DP is a standard ARM
Port (SW-DP). Even though the SW-DP interface is supported by SWJ-DP, the CC26xx and CC13xx
devices do not use this mode. The key reason is that SW-DP becomes redundant for the design in the
presence of the 2-pin JTAG (1149.7) mode.
5.3.1.2 Ordering Slave TAPs and DAPs
• When a single secondary TAP is selected, it is effectively connected to the TDO of the ICEPick TAP.
• When one or more secondary TAPs are selected, they are linked from the lowest numbered TAP to the
highest numbered TAP.
• The lowest-numbered TAP selected is connected closest to the device-level TDI (except for ICEPick),
while the highest numbered TAP is connected closest to the device TDO.
• Any selected TAPs within the test bank are linked before any TAPs within the debug bank (for
example, DAP).
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Table 5-5. Slave TAP Order
Description
DFT functionalities and profiler
RAM BIST controller interface
ROM BIST controller interface
eFuse interface for SRAM repair
PD override control/status in MCU VD
VD override control/status
DAP for CM3 debug
Section 9.1).
®
CoreSight™ debug port that combines JTAG-DP and Serial Wire Debug
Copyright © 2015, Texas Instruments Incorporated
ICEPick
Availability for End User
(1)
See
Locked
Locked
Locked
Locked
(2)
See
(2) (3)
See
Section 9.1).
399
JTAG Interface