Power Management And Sleep Modes - Texas Instruments SimpleLink CC2620 Technical Reference Manual

AES Cryptoprocessor Overview
10.1.1.1 Debug Capabilities
The AES module provides the following status registers to monitor operations of the engine:
• DMA status and port-error status registers
• Interrupt status registers in the master control module
• Key-store module status register
10.1.1.2 Exception Handling
The AES module can detect AHB master bus errors and abort the DMA operation. The AES key-store
module can detect key-load errors and does not store the bad key in that case. In both cases, the status
register in the master control module indicates the error.

10.1.2 Power Management and Sleep Modes

There is no retention logic for cryptography registers. The clocks can be enabled or gated by the following
PRCM registers:
• SECDMACLKGR.CRYPTO_CLK_EN bit while in run mode
• SECDMASCLKG.CRYPTO_CLK_EN bit while in sleep mode
• SECDMACLKGDS.CRYPTO_CLK_EN bit while in deepsleep mode
The cryptography module is enabled and disabled by the SECDMAHWOPT.CRYPTO_EN bit.
To save power, the application can disable the clock to the AES module when not in use. The AES is
clock-gated in sleep mode by setting the SECDMACLKGS register CRYPTO_CLK_EN bit. The AES can
also be clock-gated in run mode by setting the SECDMACLKGR register CRYPTO_CLK_EN bit.
10.1.3 Hardware Description
10.1.3.1 AHB Slave Bus
Internal registers of the AES module are accessed by the slave interface. The AHB slave interface
accepts 8-, 16-, and 32-bit transfers. However, the AES module accepts only 32-bit single access.
As each transfer is checked for multiple error conditions depending on the address, size, and type of the
transfer, these checks are performed on registered signals to improve timing on the input signals.
Therefore, one wait cycle must be inserted for each transfer. If an ERROR response occurs, h_ready_out
must be taken low one cycle after reception of the address. This results in the following timing:
• Write transfers take two clock cycles.
• Read transfers take three clock cycles.
The AHB slave handles only the little-endian transfers, and for register access only 32-bit single accesses
are allowed.
10.1.3.2 AHB Master Bus
The module is configured by the DMA configuration DMABUSCFG register (refer to
DMABUSCFG Register (Offset = 78h) [reset = X]) and performs single 8-bit or 32-bit nonsequential single
transfers by default. Transfer addresses and length parameters of the DMA transfer are byte aligned.
When the AES module requests a DMA transfer, the AHB master asserts and signals to indicate to the
arbiter that it requires the bus. This signal stays asserted until the address phase of the last transfer of the
DMA and no new DMA transfers are requested.
When no DMA transfers are requested, the AHB master performs IDLE transfers. If the AHB master is
already granted and gets the DMA request, the first write transfer is an IDLE transfer. The last transfer is
always an IDLE transfer.
802
Cryptography
Copyright © 2015, Texas Instruments Incorporated
Section
SWCU117C – February 2015 – Revised September 2015
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