Texas Instruments SimpleLink CC2620 Technical Reference Manual page 42

Cortex-M3 Core Registers
Bits Field Name
28 V
27 Q
26–25 ICI / IT
24 THUMB
23–16 RESERVED
15–10 ICI / IT
9–7 RESERVED
6–0 ISRNUM
42
Description
APSR Overflow Flag
Value Description
1 The previous operation resulted in an overflow.
0 The previous operation did not result in an overflow.
The value of this bit is meaningful only when accessing PSR or
APSR.
APSR Sticky Overflow and Saturation Flag
Value Description
1 Overflow or saturation has occurred. (set by SSAT
or USAT instructions).
0 Overflow or saturation has not occurred since reset
or since the bit was last cleared.
The value of this bit is meaningful only when accessing PSR or
APSR.
This flag is sticky, in that, when set by an instruction it remains set
until explicitly cleared using an MSR instruction.
EPSR ICI / IT status
These bits, along with bits 15:10, contain the ICI field for an
interrupted load multiple or store multiple instruction or the
execution state bits of the IT instruction. When EPSR holds the ICI
execution state, bits 26:25 are 0. The If-Then block contains up to
four instructions following an IT instruction. Each instruction in the
block is conditional. The conditions for the instructions are either all
the same, or some can be the inverse of others. See the Cortex™-
M3 Instruction Set Technical User's Manual for more information.
The value of this field is meaningful only when accessing PSR or
EPSR.
EPSR Thumb state
This bit indicates the Thumb state and must always be set. The
following can clear the THUMB bit:
• The BLX, BX and POP{PC} instructions
• Restoration from the stacked xPSR value on an exception return
• Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a
fault or lockup. For more information, see
The value of this bit is meaningful only when accessing PSR or
EPSR.
Reserved
EPSR ICI / IT status
These bits, along with bits 26:25, contain the ICI field for an
interrupted load multiple or store multiple instruction or the
execution state bits of the IT instruction. When an interrupt occurs
during the execution of an LDM, STM, PUSH, or POP instruction,
the processor stops the load multiple or store multiple instruction
operation temporarily and stores the next register operand in the
multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and
resumes execution of the multiple load or store instruction. When
EPSR holds the ICI execution state, bits 11:10 are 0. The If-Then
block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The
conditions for the instructions are either all the same, or some can
be the inverse of others. See the Cortex-M3/M4F Instruction Set
Technical User's Manual (SPMU159) for more information. The
value of this field is meaningful only when accessing PSR or EPSR.
Software must not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit must
be preserved across a read-modify-write operation.
IPSR ISR Number
This field contains the exception type number of the current ISR.
Value Description
0x00 Thread mode
Copyright © 2015, Texas Instruments Incorporated
Type
Section 4.2.4, Lockup.
SWCU117C – February 2015 – Revised September 2015
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R/W 0
RO 0x0
RO 1
RO 0x00
RO 0x0
RO 0x0
RO 0x00