Texas Instruments SimpleLink CC2620 Technical Reference Manual page 171

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2.7.4.31 CCR Register (Offset = D14h) [reset = 200h]
CCR is shown in Figure 2-101
Configuration Control
This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero
and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control
entry to Thread Mode.
31 30
23 22
15 14
7 6
RESERVED
R/W-0h
Bit Field
31-10 RESERVED
9 STKALIGN
8 BFHFNMIGN
7-5 RESERVED
4 DIV_0_TRP
3 UNALIGN_TRP
2 RESERVED
SWCU117C – February 2015 – Revised September 2015
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and described in Table
Figure 2-101. CCR Register
29 28
RESERVED
R/W-0h
21 20
RESERVED
R/W-0h
13 12
RESERVED
R/W-0h
5 4
DIV_0_TRP UNALIGN_TRP
R/W-0h
Table 2-127. CCR Register Field Descriptions
Type Reset Description
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 1h Stack alignment bit.
0: Only 4-byte alignment is ensured for the SP used prior to the
exception on exception entry.
1: On exception entry, the SP used prior to the exception is adjusted
to be 8-byte aligned and the context to restore it is saved. The SP is
restored on the associated exception return.
R/W 0h Enables handlers with priority -1 or -2 to ignore data BusFaults
caused by load and store instructions. This applies to the HardFault,
NMI, and FAULTMASK escalated handlers:
0: Data BusFaults caused by load and store instructions cause a
lock-up
1: Data BusFaults caused by load and store instructions are ignored.
Set this bit to 1 only when the handler and its data are in absolutely
safe memory. The normal use
of this bit is to probe system devices and bridges to detect problems.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h Enables faulting or halting when the processor executes an SDIV or
UDIV instruction with a divisor of 0:
0: Do not trap divide by 0. In this mode, a divide by zero returns a
quotient of 0.
1: Trap divide by 0. The relevant Usage Fault Status Register bit is
CFSR.DIVBYZERO.
R/W 0h Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses
1: Trap unaligned halfword and word accesses. The relevant Usage
Fault Status Register bit is CFSR.UNALIGNED.
If this bit is set to 1, an unaligned access generates a UsageFault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the value in UNALIGN_TRP.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Copyright © 2015, Texas Instruments Incorporated
Cortex-M3 Processor Registers
2-127.
27 26
19 18
11 10
3 2
RESERVED
R/W-0h R/W-0h
25 24
17 16
9 8
STKALIGN BFHFNMIGN
R/W-1h R/W-0h
1 0
USERSETMPE NONBASETHR
ND EDENA
R/W-0h R/W-0h
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