Texas Instruments SimpleLink CC2620 Technical Reference Manual page 127

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2.7.3.37 LSR Register (Offset = FB4h) [reset = 3h]
LSR is shown in Figure 2-70
Lock Status
Use this register to enable write accesses to the Control Register.
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 BYTEACC
1 ACCESS
0 PRESENT
SWCU117C – February 2015 – Revised September 2015
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and described in Table
Figure 2-70. LSR Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 2-95. LSR Register Field Descriptions
Type Reset
R 0h
R 0h
R 1h
R 1h
Copyright © 2015, Texas Instruments Incorporated
2-95.
27 26
19 18
11 10
3 2
BYTEACC
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Reads 0 which means 8-bit lock access is not be implemented.
Write access to component is blocked. All writes are ignored, reads
are permitted.
Indicates that a lock mechanism exists for this component.
Cortex-M3 Processor Registers
25 24
17 16
9 8
1 0
ACCESS PRESENT
R-1h R-1h
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