www.ti.com
6.2.1.11 XOSCHFCTL Register (Offset = 28h) [reset = 0h]
XOSCHFCTL is shown in
XOSCHF Control
31
30
23
22
15
14
7
6
RESERVED
BYPASS
R/W-0h
R/W-0h
Bit
Field
31-10
RESERVED
9-8
PEAK_DET_ITRIM
7
RESERVED
6
BYPASS
5
RESERVED
4-2
HP_BUF_ITRIM
1-0
LP_BUF_ITRIM
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Figure 6-17
and described in
Figure 6-17. XOSCHFCTL Register
29
28
RESERVED
R/W-0h
21
20
RESERVED
R/W-0h
13
12
RESERVED
R/W-0h
5
4
RESERVED
R/W-0h
Table 6-19. XOSCHFCTL Register Field Descriptions
Type
Reset
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
Copyright © 2015, Texas Instruments Incorporated
Table
6-19.
27
26
19
18
11
10
3
2
HP_BUF_ITRIM
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Power, Reset, and Clock Management
PRCM Registers
25
24
17
16
9
8
PEAK_DET_ITRIM
R/W-0h
1
0
LP_BUF_ITRIM
R/W-0h
443