VIMS Registers
7.8.1.26 SELFTESTSIGN Register (Offset = 104Ch) [reset = 0h]
SELFTESTSIGN is shown in
Internal. Only to be used through TI provided API.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Field
31-0
SIGNATURE
572
Versatile Instruction Memory System (VIMS)
Figure 7-35
and described in
Figure 7-35. SELFTESTSIGN Register
SIGNATURE
R/W-0h
Table 7-29. SELFTESTSIGN Register Field Descriptions
Type
Reset
R/W
0h
Copyright © 2015, Texas Instruments Incorporated
Table
7-29.
9
Description
Internal. Only to be used through TI provided API.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8
7
6
5
4
3
2
1
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