Texas Instruments SimpleLink CC2620 Technical Reference Manual page 206

Cortex-M3 Processor Registers
2.7.4.60 STIR Register (Offset = F00h) [reset = X]
STIR is shown in Figure 2-130
Software Trigger Interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-9 RESERVED
8-0 INTID
206
and described in Table
Figure 2-130. STIR Register
RESERVED
W-0h
Table 2-156. STIR Register Field Descriptions
Type Reset Description
W 0h
Software must not rely on the value of a reserved. Write 0.
W X
Interrupt ID field. Writing a value to this bit-field is the same as
manually pending an interrupt by setting the corresponding interrupt
bit in an Interrupt Set Pending Register in NVIC_ISPR0 or
NVIC_ISPR1.
Copyright © 2015, Texas Instruments Incorporated
2-156.
9 8 7
SWCU117C – February 2015 – Revised September 2015
www.ti.com
6 5 4 3 2 1 0
INTID
W-X
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