Texas Instruments SimpleLink CC2620 Technical Reference Manual page 423

www.ti.com
6.1.4.2.1 Clock Gating
As seen in Figure
CPU mode. The clock of a module may be enabled or disabled when the system CPU mode changes.
Example:
• PRCM:I2CCLKGR.CLK_EN = 1
• PRCM:I2CCLKGS.CLK_EN = 0
• PRCM:I2CCLKGDS.CLK_EN = 1
These settings result in the I
2
while the I C clock is disabled when system CPU is in sleep mode.
NOTE: When set in deepsleep mode, the system CPU remains in sleep mode for a few clock cycles
during the transition. An application that requires a continuous module clock enables all
clock-gate registers for the module during the transition while the system CPU changes
modes.
Because power cycling of a power domain overrides clock gate registers, disabling the module clocks
before powering down a power domain is not required.
6.1.4.2.2 Scalar to GPTs
A scalar to GPTs is available to enable GPTs to count at a slower frequency than SYSBUS clock. The
setting in the PRCM:GPTCLKDIV register is valid for all GPTs in the system.
6.1.4.2.3 Scalar to WDT
There is a scalar with a fixed-division ratio of 32 of the MCU clock that is present. Regardless of the
settings in the PRCM:INFCLKDIVR, the PRCM:INFCLKDIVS, and the PRCM:INFCLKDIVDS registers, the
watchdog counts at a constant speed, as long as the MCU clock is not changing between the SCLK_HF
and SCLK_LF as a clock source.
6.1.4.3 Clocks in AON_VD
All modules in AON_VD run on SCLK_LF except AUX_PD. Clocks to AUX_PD are user configurable.
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
6-6, the peripheral modules have conditional clock gates that depend on the system
2
C clock running when the system CPU is in run mode and deepsleep mode,
Copyright © 2015, Texas Instruments Incorporated
Power, Reset, and Clock Management
Introduction
423