Texas Instruments SimpleLink CC2620 Technical Reference Manual page 422

Introduction
SCLK_HF in active and Idle modes. Selected by
AON_WUC:MCUCLK.PWR_DWN_SRC in standby mode.
Divider
Divide by 2
SYSBUS clock gated
If SCLK_HF sources MCU clock division ratio
422
Power, Reset, and Clock Management
Figure 6-6. Clocks in MCU_VD
MCU clock
Clock gate
PRCM:RFCCLKG.CLK_EN
Clock gate
PRCM:VIMSCLKG.CLK_EN
Conditional clock gate
Clock disabled when system CPU is in SLEEP or
DEEPSLEEP. Else clock is running.
Conditional clock gate
SYSBUS clock always running except when all below is true:
- System CPU is in DEEPSLEEP
- PRCM:SECDMACLKGDS.DMA_CLK_EN = 0
- PRCM:SECDMACLKGDS.CRYPTO_CLK_EN = 0
- RFCORE FW do not require bus access
Conditional clock gate
Controlled by system CPU mode and
PRCM:SECDMACLKGR/S/DS.DMA_CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:SECDMACLKGR/S/DS.CRYPTO_CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:SECDMACLKGR/S/DS.TRNG_CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:GPTCLKGR/S/DS.CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:GPIOCLKGR/S/DS.CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:I2SCLKGR/S/DS.CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:SSICLKGR/S/DS.CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:UARTCLKGR/S/DS.CLK_EN
Conditional clock gate
Controlled by system CPU mode and
PRCM:I2CCLKGR/S/DS.CLK_EN
Conditional divider
Controlled by system CPU mode and
PRCM:INFCLKDIVR/S/DS
is overridden to 2 if
PRCM:INFCLKDIVR/S/ DS = 1
Copyright © 2015, Texas Instruments Incorporated
SCLK_HF
SCLK_LF
SYSBUS clock
PERBUSULL clock
0
1
0
INFRASTRUCTURE clock
SWCU117C – February 2015 – Revised September 2015
www.ti.com
RFCORE_PD
VIMS_PD
CPU_PD
BUS_PD
PERIPH_PD
DMA controller
CRYPTO core
True random number gen.
GPT [3:0]
GPIO
I2S
SSI1
SERIAL_PD
SSI0
UART
2
I C
MCU_AON
AON interface
Event fabric
I/O controller
Wakeup interrupt controller
Watchdog timer
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