Texas Instruments SimpleLink CC2620 Technical Reference Manual page 453

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6.2.2.2 RESETCTL Register (Offset = 4h) [reset = E0h]
RESETCTL is shown in
Reset Management
This register contains bitfields releated to system reset such as reset source and reset request and control
of brown out resets.
31 30
SYSRESET
W-0h
23 22
15 14
WU_FROM_SD GPIO_WU_FR
OM_SD
R-0h R-0h
7 6
VDDS_LOSS_ VDDR_LOSS_
EN EN
R/W-1h R/W-1h
Bit Field
31 SYSRESET
30-26 RESERVED
25 BOOT_DET_1_CLR
24 BOOT_DET_0_CLR
23-18 RESERVED
17 BOOT_DET_1_SET
16 BOOT_DET_0_SET
15 WU_FROM_SD
SWCU117C – February 2015 – Revised September 2015
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Figure 6-24 and described in
Figure 6-24. RESETCTL Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
BOOT_DET_1 BOOT_DET_0
R-0h R-0h
5 4
VDD_LOSS_E CLK_LOSS_EN
N
R/W-1h R/W-0h
Table 6-27. RESETCTL Register Field Descriptions
Type Reset
W 0h
R 0h
R/W 0h
R/W 0h
R 0h
R/W 0h
R/W 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-27.
27 26
19 18
11 10
VDDS_LOSS_ VDDR_LOSS_
EN_OVR EN_OVR
R/W-0h R/W-0h
3 2
RESET_SRC
R-0h
Description
Cold reset register. Writing 1 to this bitfield will reset the entire chip
and cause boot code to run again.
0: No effect
1: Generate system reset. Appears as SYSRESET in RESET_SRC.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
A Wakeup from SHUTDOWN on an IO event has occurred, or a
wakeup from SHUTDOWN has occurred as a result of the debugger
being attached.. (TCK pin being forced low)
Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as
wakeup sources.
0: Wakeup occurred from cold reset or brown out as seen in
RESET_SRC
1: A wakeup has occurred from SHUTDOWN
Note: This flag can not be cleared and will therefor remain valid untill
poweroff/reset
Power, Reset, and Clock Management
PRCM Registers
25 24
BOOT_DET_1_ BOOT_DET_0_
CLR CLR
R/W-0h R/W-0h
17 16
BOOT_DET_1_ BOOT_DET_0_
SET SET
R/W-0h R/W-0h
9 8
VDD_LOSS_E RESERVED
N_OVR
R/W-0h R-0h
1 0
RESERVED
R-0h
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