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4.7.2.46 GPT0BCAPTSEL Register (Offset = 204h) [reset = 56h]
GPT0BCAPTSEL is shown in
Output Selection for GPT0 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Field
31-7
RESERVED
SWCU117C – February 2015 – Revised September 2015
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Figure 4-55
and described in
Figure 4-55. GPT0BCAPTSEL Register
RESERVED
R-0h
Table 4-60. GPT0BCAPTSEL Register Field Descriptions
Type
Reset
R
0h
Copyright © 2015, Texas Instruments Incorporated
Table
4-60.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Interrupts and Events Registers
8
7
6
5
4
3
2
1
EV
R/W-56h
Interrupts and Events
0
321