Texas Instruments SimpleLink CC2620 Technical Reference Manual page 510

PRCM Registers
6.2.4.35 I2SWCLKDIV Register (Offset = DCh) [reset = 0h]
I2SWCLKDIV is shown in
WCLK Division Ratio
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bit Field
31-16 RESERVED
15-0 WDIV
510
Power, Reset, and Clock Management
Figure 6-74 and described in
Figure 6-74. I2SWCLKDIV Register
R-0h
Table 6-79. I2SWCLKDIV Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-79.
9
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
If I2SCLKCTL.WCLK_PHASE = 0, Single phase.
WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-
1023]) BCLK periods.
WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]
MCUCLK is 48MHz in normal mode. For powerdown mode the
frequency is defined by AON_WUC:MCUCLK.PWR_DWN_SRC
If I2SCLKCTL.WCLK_PHASE = 1, Dual phase.
Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-
1023]) BCLK periods.
WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz]
If I2SCLKCTL.WCLK_PHASE = 2, User defined.
WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low
WDIV[15:8] (unsigned, [1-255]) BCLK periods.
WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]
For changes to take effect, CLKLOADCTL.LOAD needs to be written
SWCU117C – February 2015 – Revised September 2015
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8 7 6 5 4 3 2 1
WDIV
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