Texas Instruments SimpleLink CC2620 Technical Reference Manual page 208

Cortex-M3 Processor Registers
2.7.5.1 SSPSR Register (Offset = 0h) [reset = Bh]
SSPSR is shown in
Supported Sync Port Sizes
This register represents a single port size that is supported on the device, that is, 4, 2 or 1. This is to
ensure that tools do not attempt to select a port width that an attached TPA cannot capture.
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3 FOUR
2 THREE
1 TWO
0 ONE
208
Figure 2-131 and described in
Figure 2-131. SSPSR Register
29 28
21 20
13 12
5 4
R-0h
Table 2-158. SSPSR Register Field Descriptions
Type Reset
R 0h
R 1h
R 0h
R 1h
R 1h
Copyright © 2015, Texas Instruments Incorporated
Table 2-158.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
FOUR THREE
R-1h R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
4-bit port size support
0x0: Not supported
0x1: Supported
3-bit port size support
0x0: Not supported
0x1: Supported
2-bit port size support
0x0: Not supported
0x1: Supported
1-bit port size support
0x0: Not supported
0x1: Supported
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
TWO
R-1h
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24
16
8
0
ONE
R-1h