Texas Instruments SimpleLink CC2620 Technical Reference Manual page 207

www.ti.com
2.7.5 CPU_TPIU Registers
Table 2-157 lists the memory-mapped registers for the CPU_TPIU. All register offset addresses not listed
in Table 2-157 must be considered as reserved locations and the register contents must not be modified.
Offset Acronym
0h SSPSR
4h CSPSR
10h ACPR
F0h SPPR
300h FFSR
304h FFCR
308h FSCR
FA0h CLAIMMASK
FA0h CLAIMSET
FA4h CLAIMTAG
FA4h CLAIMCLR
FC8h DEVID
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Table 2-157. CPU_TPIU Registers
Register Name
Supported Sync Port Sizes
Current Sync Port Size
Async Clock Prescaler
Selected Pin Protocol
Formatter and Flush Status
Formatter and Flush Control
Formatter Synchronization Counter
Claim Tag Mask
Claim Tag Set
Current Claim Tag
Claim Tag Clear
Device ID
Copyright © 2015, Texas Instruments Incorporated
Cortex-M3 Processor Registers
Section
Section 2.7.5.1
Section 2.7.5.2
Section 2.7.5.3
Section 2.7.5.4
Section 2.7.5.5
Section 2.7.5.6
Section 2.7.5.7
Section 2.7.5.8
Section 2.7.5.9
Section 2.7.5.10
Section 2.7.5.11
Section 2.7.5.12
207