Texas Instruments SimpleLink CC2620 Technical Reference Manual page 459

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6.2.3.2 AUXCLK Register (Offset = 4h) [reset = 1h]
AUXCLK is shown in
AUX Clock Management
This register contains bitfields that are relevant for setting up the clock to the AUX domain.
31 30
23 22
15 14
RESERVED
R-0h
7 6
Bit Field
31-13 RESERVED
12-11 PWR_DWN_SRC
10-8 SCLK_HF_DIV
7-3 RESERVED
2-0 SRC
SWCU117C – February 2015 – Revised September 2015
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Figure 6-27 and described in
Figure 6-27. AUXCLK Register
29 28
RESERVED
21 20
RESERVED
13 12
PWR_DWN_SRC
5 4
RESERVED
R-0h
Table 6-31. AUXCLK Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R 0h
R/W 1h
Copyright © 2015, Texas Instruments Incorporated
Table 6-31.
27 26
R-0h
19 18
R-0h
11 10
R/W-0h
3 2
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
When AUX requests powerdown with SCLK_HF as source, then
WUC will switch over to this clock source during powerdown, and
automatically switch back to SCLK_HF when AUX system is back in
active mode
0h = No clock in Powerdown
1h = Use SCLK_LF in Powerdown
Select the AUX clock divider for SCLK_HF
NB: It is not supported to change the AUX clock divider while
SCLK_HF is active source for AUX
0h = Divide by 2
1h = Divide by 4
2h = Divide by 8
3h = Divide by 16
4h = Divide by 32
5h = Divide by 64
6h = Divide by 128
7h = Divide by 256
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Selects the clock source for AUX:
NB: Switching the clock source is guaranteed to be glitchless
1h = HF Clock (SCLK_HF)
4h = LF Clock (SCLK_LF)
Power, Reset, and Clock Management
PRCM Registers
25 24
17 16
9 8
SCLK_HF_DIV
R/W-0h
1 0
SRC
R/W-1h
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