Texas Instruments SimpleLink CC2620 Technical Reference Manual page 491

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6.2.4.16 GPTCLKGDS Register (Offset = 5Ch) [reset = 0h]
GPTCLKGDS is shown in
GPT Clock Gate For Deep Sleep Mode
31 30 29 28
15 14 13 12
Bit Field
31-4 RESERVED
3-0 CLK_EN
SWCU117C – February 2015 – Revised September 2015
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Figure 6-55 and described in
Figure 6-55. GPTCLKGDS Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-60. GPTCLKGDS Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-60.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Each bit below has the following meaning:
0: Disable clock
1: Enable clock
ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for GPT0
2h = Enable clock for GPT1
4h = Enable clock for GPT2
8h = Enable clock for GPT3
Power, Reset, and Clock Management
PRCM Registers
19 18 17 16
3 2 1 0
CLK_EN
R/W-0h
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