Texas Instruments SimpleLink CC2620 Technical Reference Manual page 125

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Bit Field
1 TSENA
0 ITMENA
SWCU117C – February 2015 – Revised September 2015
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Table 2-93. TCR Register Field Descriptions (continued)
Type Reset
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Description
Enables differential timestamps. Differential timestamps are emitted
when a packet is written to the FIFO with a non-zero timestamp
counter, and when the timestamp counter overflows. Timestamps
are emitted during idle times after a fixed number of two million
cycles. This provides a time reference for packets and inter-packet
gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity
on the internal trace bus only. In this case there is no regular
timestamp output when the ITM is idle.
Enables ITM. This is the master enable, and must be set before ITM
Stimulus and Trace Enable registers can be written.
Cortex-M3 Processor Registers
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