Texas Instruments SimpleLink CC2620 Technical Reference Manual page 336

Interrupts and Events Registers
4.7.2.51 UDMACH1SSEL Register (Offset = 508h) [reset = 31h]
UDMACH1SSEL is shown in
Output Selection for DMA Channel 1 SREQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-7 RESERVED
6-0 EV
336
Interrupts and Events
Figure 4-60 and described in
Figure 4-60. UDMACH1SSEL Register
RESERVED
R-0h
Table 4-65. UDMACH1SSEL Register Field Descriptions
Type Reset
R 0h
R 31h
Copyright © 2015, Texas Instruments Incorporated
Table 4-65.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Read only selection value
31h = UART0 RX DMA single request, controlled by
UART0:DMACTL.RXDMAE
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
EV
R-31h
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