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Texas Instruments SimpleLink CC2620 Technical Reference Manual page 128

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Cortex-M3 Processor Registers
2.7.4 CPU_SCS Registers
Table 2-96
lists the memory-mapped registers for the CPU_SCS. All register offset addresses not listed in
Table 2-96
must be considered as reserved locations and the register contents must not be modified.
Offset
Acronym
4h
ICTR
8h
ACTLR
10h
STCSR
14h
STRVR
18h
STCVR
1Ch
STCR
100h
NVIC_ISER0
104h
NVIC_ISER1
180h
NVIC_ICER0
184h
NVIC_ICER1
200h
NVIC_ISPR0
204h
NVIC_ISPR1
280h
NVIC_ICPR0
284h
NVIC_ICPR1
300h
NVIC_IABR0
304h
NVIC_IABR1
400h
NVIC_IPR0
404h
NVIC_IPR1
408h
NVIC_IPR2
40Ch
NVIC_IPR3
410h
NVIC_IPR4
414h
NVIC_IPR5
418h
NVIC_IPR6
41Ch
NVIC_IPR7
420h
NVIC_IPR8
D00h
CPUID
D04h
ICSR
D08h
VTOR
D0Ch
AIRCR
D10h
SCR
D14h
CCR
D18h
SHPR1
D1Ch
SHPR2
D20h
SHPR3
D24h
SHCSR
D28h
CFSR
D2Ch
HFSR
D30h
DFSR
D34h
MMFAR
D38h
BFAR
D3Ch
AFSR
D40h
ID_PFR0
D44h
ID_PFR1
D48h
ID_DFR0
128
Table 2-96. CPU_SCS Registers
Register Name
Interrupt Control Type
Auxiliary Control
SysTick Control and Status
SysTick Reload Value
SysTick Current Value
SysTick Calibration Value
Irq 0 to 31 Set Enable
Irq 32 to 63 Set Enable
Irq 0 to 31 Clear Enable
Irq 32 to 63 Clear Enable
Irq 0 to 31 Set Pending
Irq 32 to 63 Set Pending
Irq 0 to 31 Clear Pending
Irq 32 to 63 Clear Pending
Irq 0 to 31 Active Bit
Irq 32 to 63 Active Bit
Irq 0 to 3 Priority
Irq 4 to 7 Priority
Irq 8 to 11 Priority
Irq 12 to 15 Priority
Irq 16 to 19 Priority
Irq 20 to 23 Priority
Irq 24 to 27 Priority
Irq 28 to 31 Priority
Irq 32 to 35 Priority
CPUID Base
Interrupt Control State
Vector Table Offset
Application Interrupt/Reset Control
System Control
Configuration Control
System Handlers 4-7 Priority
System Handlers 8-11 Priority
System Handlers 12-15 Priority
System Handler Control and State
Configurable Fault Status
Hard Fault Status
Debug Fault Status
Mem Manage Fault Address
Bus Fault Address
Auxiliary Fault Status
Processor Feature 0
Processor Feature 1
Debug Feature 0
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
www.ti.com
Section
Section 2.7.4.1
Section 2.7.4.2
Section 2.7.4.3
Section 2.7.4.4
Section 2.7.4.5
Section 2.7.4.6
Section 2.7.4.7
Section 2.7.4.8
Section 2.7.4.9
Section 2.7.4.10
Section 2.7.4.11
Section 2.7.4.12
Section 2.7.4.13
Section 2.7.4.14
Section 2.7.4.15
Section 2.7.4.16
Section 2.7.4.17
Section 2.7.4.18
Section 2.7.4.19
Section 2.7.4.20
Section 2.7.4.21
Section 2.7.4.22
Section 2.7.4.23
Section 2.7.4.24
Section 2.7.4.25
Section 2.7.4.26
Section 2.7.4.27
Section 2.7.4.28
Section 2.7.4.29
Section 2.7.4.30
Section 2.7.4.31
Section 2.7.4.32
Section 2.7.4.33
Section 2.7.4.34
Section 2.7.4.35
Section 2.7.4.36
Section 2.7.4.37
Section 2.7.4.38
Section 2.7.4.39
Section 2.7.4.40
Section 2.7.4.41
Section 2.7.4.42
Section 2.7.4.43
Section 2.7.4.44

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