Texas Instruments SimpleLink CC2620 Technical Reference Manual page 144

Cortex-M3 Processor Registers
2.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [reset = 0h]
NVIC_ISPR0 is shown in
Irq 0 to 31 Set Pending
This register is used to force interrupts into the pending state and determine which interrupts are currently
pending.
31 30
SETPEND31 SETPEND30
R/W-0h R/W-0h
23 22
SETPEND23 SETPEND22
R/W-0h R/W-0h
15 14
SETPEND15 SETPEND14
R/W-0h R/W-0h
7 6
SETPEND7 SETPEND6
R/W-0h R/W-0h
Bit Field
31 SETPEND31
30 SETPEND30
29 SETPEND29
28 SETPEND28
27 SETPEND27
26 SETPEND26
25 SETPEND25
24 SETPEND24
23 SETPEND23
22 SETPEND22
21 SETPEND21
144
Figure 2-81 and described in
Figure 2-81. NVIC_ISPR0 Register
29 28
SETPEND29 SETPEND28
R/W-0h R/W-0h
21 20
SETPEND21 SETPEND20
R/W-0h R/W-0h
13 12
SETPEND13 SETPEND12
R/W-0h R/W-0h
5 4
SETPEND5 SETPEND4
R/W-0h R/W-0h
Table 2-107. NVIC_ISPR0 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-107.
27 26
SETPEND27 SETPEND26
R/W-0h R/W-0h
19 18
SETPEND19 SETPEND18
R/W-0h R/W-0h
11 10
SETPEND11 SETPEND10
R/W-0h R/W-0h
3 2
SETPEND3 SETPEND2
R/W-0h R/W-0h
Description
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current state.
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current state.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
SETPEND25 SETPEND24
R/W-0h R/W-0h
17 16
SETPEND17 SETPEND16
R/W-0h R/W-0h
9 8
SETPEND9 SETPEND8
R/W-0h R/W-0h
1 0
SETPEND1 SETPEND0
R/W-0h R/W-0h
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