www.ti.com
2.7.4.2
ACTLR Register (Offset = 8h) [reset = 0h]
ACTLR is shown in
Auxiliary Control
This register is used to disable certain aspects of functionality within the processor
31
30
23
22
15
14
7
6
Bit
Field
31-3
RESERVED
2
DISFOLD
1
DISDEFWBUF
0
DISMCYCINT
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Figure 2-72
and described in
Figure 2-72. ACTLR Register
29
28
21
20
13
12
5
4
RESERVED
R/W-0h
Table 2-98. ACTLR Register Field Descriptions
Type
Reset
R/W
0h
R/W
0h
R/W
0h
R/W
0h
Copyright © 2015, Texas Instruments Incorporated
Table
2-98.
27
RESERVED
R/W-0h
19
RESERVED
R/W-0h
11
RESERVED
R/W-0h
3
DISFOLD
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Disables folding of IT instruction.
Disables write buffer use during default memory map accesses. This
causes all bus faults to be precise bus faults but decreases the
performance of the processor because the stores to memory have to
complete before the next instruction can be executed.
Disables interruption of multi-cycle instructions. This increases the
interrupt latency of the processor becuase LDM/STM completes
before interrupt stacking occurs.
Cortex-M3 Processor Registers
26
25
18
17
10
9
2
1
DISDEFWBUF
DISMCYCINT
R/W-0h
24
16
8
0
R/W-0h
131