Texas Instruments SimpleLink CC2620 Technical Reference Manual page 515

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6.2.4.40 PDCTL0SERIAL Register (Offset = 134h) [reset = 0h]
PDCTL0SERIAL is shown in
SERIAL Power Domain Control
31 30 29 28
15 14 13 12
Bit Field
31-1 RESERVED
0 ON
SWCU117C – February 2015 – Revised September 2015
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Figure 6-79 and described in
Figure 6-79. PDCTL0SERIAL Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-84. PDCTL0SERIAL Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-84.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Alias for PDCTL0.SERIAL_ON
Power, Reset, and Clock Management
PRCM Registers
19 18 17 16
3 2 1 0
ON
R/W-
0h
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